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| 1424f?rke?12/03 features rf frequency range of 264?456 mhz 6 dbm rf output into matched antenna rf output power adjustable over 36 db with 1 db resolution phase-locked loop (pll) based frequency synthesizer supports ook modulation data bandwidth of up to 10 kbps manchester 2-volt operation 8-bit avr ? ? ? ? risc microcontroller core minimal external components space-saving 20-lead tssop 2 kb (1k x 16) of flash program memory 128 bytes of eeprom 128 bytes of sram in-system programmable data and program memory six i/os (serial i/f, led drive outputs, button input interrupts) low battery detect and brown-out protection software fine-tuning of vco tank circuit applications remote keyless entry (rke) transmitters wireless security systems home applicance control (lighting control, ceiling fans) radio remote control (hobby, toys) garage door openers wireless pc peripherals (keyboard, mouse) telemetry (tire pressure, utility meter, asset tracking) description the atmel AT86RF401 smart rf microtransmitter is a hi ghly int egrated, low-cost rf transmitter, combined with an avr risc microcontroller. it requires only a crystal, a single limno 2 coin cell (cr2032 or similar), three capacitors, an inductor and a tuned- loop antenna to implement a complete on-off keyed (oof) wireless rf data transmitter. figure 1. block diagram phase detector oscillator loop filter vco prescaler 24 rf amp loop fil clock reset watchdog low-voltage detect brown-out protect avr ? risc c 2 kb flash program memory 128 bytes eeprom data memory l1 l2 data gain trim power supply supervisor xtal/clk xtalb avdd agnd ant antb b + dvdd dgnd io5 io4 io3 sck/io2 sdo/io1 sdi/io0 resetb smart rf wireless data microtransmitter AT86RF401
2 AT86RF401 1424f ? rke ? 12/03 in-system programmable, nonvolatile flash program memory and eeprom data stor- age make possible rapid time-to-market and lower inventory costs. in-system programmable, nonvolatile flash program memory and eeprom data stor- age make possible rapid time-to-market and lower inventory costs.in-system programmable, nonvolatile flash program memory and eeprom data storage make possible rapid time-to-market and lower inventory costs.static current consumption is kept to a minimum with an ultra-low cu rrent shutdown mode. normal operation resumes when a button is pressed. this activates the crystal oscillator circuit that serves as the clock for the avr microcontroller. the rf carrier is synthesized utilizing an on-board voltage controlled oscillator (vco). optimal tuning of the vco is maintained over component tolerance thr ough the use of a software-controlled switched capacitor array. its accuracy is maintained with a pll detector that compares the crystal oscillator to a frequency-scaled version (divided by 24) of the rf carrier. the resulting error signal adju sts the vco to pr oduce a very stable rf carrier. an interrupt-based bit-timer structure, integral to the avr microcontroller, simplifies the implementation of user-specific, data-bit encoding routines, such as pwm or manches- ter, for modulating the rf carrier. thirty-six db of rf power output control is available to the user in 1 db steps and is addressable in software. the rf signal output is placed dif- ferentially on a tuned-loop antenna, which may be realized as a counterspread copper trace on a pcb. the AT86RF401 is fabricated in atmel ? s 0.6 m mixed signal cmos + eeprom pro- cess, enabling true system-level integration (sli). figure 2. 20-lead tssop 1 2 3 4 5 6 7 8 9 10 antb loopfil l1 l2 resetb n/c i/o0 (sdi) i/o1 (sdo) i/o2 (sck) xtal/clk 20 19 18 17 16 15 14 13 12 11 ant n/c avdd dvdd agnd dgnd i/o5 i/o4 i/o3 xtalb 3 AT86RF401 1424f ? rke ? 12/03 figure 3. sample circuit table 1 . recommended parts list part number value (common) value (315 mhz) value (433.92 mhz) value (ext. loop filter) specification b1 3.6v cr2032, li battery c1 0.01 f 0603, x7r, 10% c2 100 pf 0603, cog, 5% c3 antenna dependent antenna dependent antenna dependent 0603, cog, 0.1 pf c4 not req ? d not req ? d frequency dependent 0603, cog, 5% c5 not req ? d not req ? d frequency dependent 0603, cog, 0.25 pf l1 82 nh 39 nh frequency dependent 1608, 5% r1 not req ? d not req ? d frequency dependent 0603, 5% s1 switch spst s2 switch spst s3 switch spst u1 AT86RF401 20-lead tssop y1 13.125 mhz 18.08 mhz frequency dependent 13.125 mhz: crystek ? p/n 016757 18.080 mhz: crystek p/n 016758 antb loopfil l1 l2 resetb nc io0/sdi io1/sdo io2/sclk xtal/clk ant nc avdd dvdd agnd dgnd io5 io4 io3 xtalb s1 s2 s 3 y1 reset sdo sdi sclk u1 v+ c3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 r1 c4 c5 v+ c2 c1 b1 spi programming interface l1 external loop filter (optional) 4 AT86RF401 1424f ? rke ? 12/03 table 2 . pin descriptions ? 20-lead tssop symbol pin description antb 1 differential antenna output loopfil 2 external vco loop-filter connection. v vco is the vco control voltage. l1 3 external vco inductor connection. v vco is the vco control voltage. l2 4 external vco inductor connection. v vco is the vco control voltage. 120 10 ma v dd v dd v vco 2 4 3 v dd v dd v vco 2 4 3 v dd v dd v vdd 2 4 3 5 AT86RF401 1424f ? rke ? 12/03 resetb 5 spi reset input: a ? low ? on this pin resets the device and puts the part into spi mode. a logic-high on this pin causes the device to execute its program if the v dd is above the brown- out voltage level. nc 6 no connect. float pin. i/o0 (sdi) 7 spi data in/input/output 0: general-purpose i/o and button input. in spi mode, this pin serves as sdi (serial data input). i/o1 (sdo) 8 spi data out/input/output 1: general-purpose i/o and button input. in spi mode, this pin serves as sdo (se rial data output). i/o2 (sck) 9 spi clock/input/output 2: general-purpose i/o and button input. in spi mode, this pin serves as sck (spi clock input). xtal/clk 10 crystal/clock input: input to the inverting oscillator amplifier and input to the internal clock operating circuit. this pin may be driven externally for test purposes. table 2 . pin descriptions ? 20-lead tssop (continued) v dd 35 k ? 5 to av r v dd v dd data nable ? data enable 7 35 k ? to av r v dd v dd data enable ? data enable 8 35 k ? to av r v dd v dd data enable ? data enable 9 35 k ? to av r 40 pf 40 pf 10 11 6 AT86RF401 1424f ? rke ? 12/03 xtalb 11 crystal output: output from the inverting oscillator amplifier io3 12 input/output 3: general-purpose i/o and button input io4 13 input/output 4: general-purpose i/o and button input io5 14 input/output 5: general-purpose i/o and button input dgnd 15 digital ground agnd 16 analog ground dvdd 17 digital voltage supply table 2 . pin descriptions ? 20-lead tssop (continued) 40 pf 40 pf 10 11 v dd v dd data enable data enable 12 35 k ? to av r v dd v dd data enable data enable 13 35 k ? to av r v dd v dd data enable data enable 14 35 k ? to av r 7 AT86RF401 1424f ? rke ? 12/03 avdd 18 analog voltage supply n/c 19 no connect ? float pin ant 20 differential antenna output table 2 . pin descriptions ? 20-lead tssop (continued) 120 10 ma 8 AT86RF401 1424f ? rke ? 12/03 absolute maximum ratings* antenna voltage (pins 1, 20) ...................................... ? 1v to 10v *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only; functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating temperature ........................................? 40 c to +85 c storage temperature (without bias) ................? 55 c to +125 c voltage on v dd with respect to ground ............................. 6.0v voltage on pins 2 ? 19 (tssop 20) ................ ? 0.1 to v dd +0.3v table 3 . dc characteristics v dd = 3.3v; f xtal = 13.125 mhz; f avr = f xtal 16; t a = 25 c unless otherwise specified. symbol parameter conditions min typ max unit supply v dd supply voltage 2.0 3.3 5.0 v i dd standby current (off) v dd = 3.3v t a = 25 c ? 0.1 0.5 a avr active ? 3.4 ? ma frequency synthesizer + avr active ? 14.3 ? ma transmit (fs, avr and power amp active) cw modulation ? 23.2 ? ma digital inputs (sdi, sck, resetb, iox) v ih high-level input voltage 0.8* v dd ? v dd v v il low-level input voltage 0 ? 0.2* v dd v i ih high-level input current v ih = v dd , v dd = 5.0v ? ? 1 a i il low-level input current v il = 0v , v dd = 5.0v ? 140 ? ? a digital outputs (sdo, iox) v oh high-level output voltage i oh = ? 500 a v dd ? 0.4 ? ? v v ol low-level output voltage i ol = 2 ma ? ? 0.4 v microcontroller/system t tx time from button wake-up to rf outputs active ? 0.5 1.0 ms f avr avr clock frequency ? ? 1.25 mhz ee life eeprom retention initial programming conditions: v dd = 3.3v 10% temp = 25 c 10% ? ? 10 years ee cycles eeprom write/erase endurance 2.0v v dd 5.0v ? 40 c te m p 85 c ? ? 100,000 cycles 9 AT86RF401 1424f ? rke ? 12/03 note: 1. characterized but not guaranteed by test due to dependency on pcb trace antenna functional description the complete circuit consists of the following functional blo cks. transmitter crystal oscillator the crystal oscillator circuit is designed to work with crystals w ith fundamental frequen- cies between 11 and 19 mhz. forty pf of internal capacitance is connected between each of the crystal i nput pins and (chip) ground. alternatively, an external clock can be used for these functions. this circuit provides the master clock for the entire chip. a programmable divider is used to provide the avr system clock. radio frequency power amplifier the rf power amplifier generates a differential output suitable for driving an off-chip tuned-loop antenna from the pll o utput. the pll output signal is gated using o n-off keyed (ook) modulation before transmission. it is used as the rf carrier frequency for the transmitted data stream. the amplifier can be configured via software to reduce the power output by 36 db (with 1 db resolution). frequency synthesizer the frequency synthesizer utilizes a pll, which consists of a phase detector, a 24 prescaler, an on-chip l oop fil ter and an in tegrated vco. the vco output is buffered prior to the output amplifier. the output frequency is 24 times the crystal frequency. to offset component tolerance, a switched capacitor array is connected between pins 3 and 4 of the vco. thirty-two discrete steps of capacitance are available to tune the vco control voltage. an internal window comparator monitors the magnitude of the tun- ing voltage and is used by the avr core to determine the optimal tuning configurat ion. lock detector the lock detection block provides an indication of the state of the phase lock loop (pll). lock condition is determined by counting the number of cycle slips in a given time table 4 . analog/rf specs v dd = 3.3v; f xtal = 13.125 mhz; f avr = f xtal 16; t a = 25 c unless otherwise specified. symbol parameter conditions min typ max unit rf amplifier i pa power amp output current transmitting (rf ? on ? ), 0 db attenuation ? 8.6 ? ma p ctlrange power control range ? 36 ? db p ctlres power control resolution ? 1 ? db crystal oscillator f osc oscillation freq uency range 11 ? 19 mhz frequency synthesizer/pll f out output frequency range 264 ? 456 mhz p harm 1 harmonics i/o pins static during rf transmission using pcb trace antenna ? ? 60 ? dbc f mod ook modulation data rate using manchester data bit encoding ? ? 10 kbps 10 AT86RF401 1424f ? rke ? 12/03 period. a number of registers are available to adjust the performance of the lock detec- tor. these include lock delay and unlock delay timers as well as a cycle slip counter. bandgap reference the device uses a 1.2v (nominal) bandgap reference generator to provide consistent performance over a wide range of input supply voltages. this reference voltage is used throughout the device. brown-out protection/low battery detection the brown-out protection and low battery detection functions consist of a voltage refer- ence, a sampling block and an autozero comparator. the circuit ? s primary operating mode is brown-out protection. brown-out protection the brown-out protection circuit detects when the level of v dd drops below the minimum voltage that guarantees proper operation. the brown-out voltage for this device is typi- cally 1.8 volts. if a brown-out occurs, the device enters a reset state. it stays in this state until either of the following occurs: the level of v dd increases ~0.1 ? 0.2 volts above the brown-out volt age. this causes the device to enter a warm r eboot state. the level of v dd drops to ~0 volts, then increases above the por level. this pl aces the device into the ? cold start ? mode of operation, identical to battery insertion. low battery detection the low battery detection feature allows the programmer to select a voltage threshold (1.5 ? 2.7 volts) for v dd at which a warning flag is issued to the user. for example, this warning may be utilized to activate an i/o port or to change the transmitted message. additionally, the programmer has the option of defining the amount of hysteresis on this threshold. more detail can be found in register descriptions for i/o enable (io_enab, $30, page 39) and battery low configuration (bl_con fig, $35, page 42). 11 AT86RF401 1424f ? rke ? 12/03 bit timer a hardware assist has been included in the at 8 6 r f 4 0 1 to make transmission of data easier. keying of the transmitter is timed by this logic, and interrupts are generated when data is needed by the timer or when transmission is complete. the timer also sup- ports code that uses polling instead of interrupts. using polling inst ead of interrupts may facilitate higher bit rates. additionally, this timer may be used to time pulses arriving at the i/o3 pin. this enables the AT86RF401 to be used to decode the signal detected by an external receiver chip. for additional information on how to implement the bit timer, see AT86RF401 bit timer application note, available at www.atmel.com. bit timer in transmit mode bit coding is done by the avr before data is sent to the bit timer. bit timing is controlled by the count value in the bit timer count (btcnt) register and the two most significant bits in the bit timer control register (btcr). generally the time of each bit is: where p xx is the period of each time slot and countval is the counter value in the btcnt and btcr registers. p is the avr clock period that is set in the pwr_ctl register. countval = {btcr[7:6], btcnt[7:0]}. there are two interrupts associated with transmit mode: 1. transmit buffer empty interrupt: this vectors to address 0x04. flag 0 is set, and, if enabled, this interrupt is generated when the timer removes the value from the data bit in the btcr. this interrupt service routine should load the next transmit bit into the data bit in the btcr. 2. txdone interrupt: this vectors to address 0x02. flag 2 is set, and, if enabled, an interrupt is generated when the counter has counted down to zero and the buffer is empty. this indicates that the transmission is compl ete. this interrupt service routine should turn off the transmitter and turn off the bit timer using the mode bits. bit timer in receive mode when put into receive mode, the bit timer times pulses arriving at the i/o3 pin. when enabled, the counter counts up from zero and places that value in the btcnt register when an edge occurs. if the edge is rising, the data bit in the btcr is set. if the edge is falling, the data bit in the btcr is reset. this mode may be used to decode signals from a receiver chip easily. bit timer in generic timer/counter mode the bit timer may be used as a generic timer by not allowing it to key off the transm itter. an interrupt is generated after the amount of time dictated by the count value. p xx p countval 1 + () = 12 AT86RF401 1424f ? rke ? 12/03 watchdog timer when enabling the watchdog timer, the status of the watchdog time is unknown. the user is advised to execute a wdr instruction before enabling the watchdog. otherw ise, the device might get reset before the first wdr after enabling is reached. to prevent the unintentional disabling of the watchdog, a spe cial turn-off procedure must be fol lowed when the watchdog is disabled. refer to the description of the watchdog timer control register on page 38 for details (see register $22 in i/o memory). the watchdog timer prescaler determines the number of system clocks that occur before the watchdog reset is asserted. the system clock is determined by bits[7:5] of the avr_config register. reset and interrupt handling the AT86RF401 reset and interrupt vectors are defined in table 5. the i-bit in the sta- tus register must be set to enable the interrupts. the most typical and general program setup for the reset and interrupt vector addresses are: reset sources the AT86RF401 has several sources of reset: power-on reset: the device is reset when the supply voltage is applied between the vdd and gnd pins. there are 10 6 cycles of delay between power-on reset occurring and the part becoming active. this is to ensure that the power is stable. external reset: the device is reset when a logic low level is present on the resetb pin. this resets all i/o registers and puts the part into spi mode. the i/o registers may be read and written by the spi interface after two avr system clocks. watchdog reset: this is similar to power-on reset but is caused by the watchdog timer and does not have a 10 6 cycle delay prior to becoming active. brown-out reset: this is caused by the battery voltage dropping below the brown- out threshold voltage trip point. button reset (software reset): the part is placed into a special reset state by software. the part is released from reset when a properly configured button is activated, and the part is not in external reset or brown-out res et. in the button reset state, most i/o registers are not reset, and t here is no time delay before becoming active. ta ble 5. reset and interrupt vectors vector number program address source interrupt definition 1 $000 resetb, watchdog, buttons hardware pin or watc hdog or button reset 2 $002 transmission done (txdone) bit timer flag 2 interrupt 4 $004 transmit buffer empty bit timer flag 0 interrupt address labels code comments $000 jmp reset ; reset handler $002 jmp bt_f2_isr ; bit timer flag 2 interrupt service routine $004 jmp bt_f0_isr ; bit timer flag 0 interrupt service routine $006 main: 13 AT86RF401 1424f ? rke ? 12/03 during power-on reset and watc hdog reset, all i/o registers are set to their initial values, and the program starts execution from address $0 00. note: the instruction placed in address $000 must be an rjmp (relative jump) instruction or a jmp (absolute jump) to the reset handling routine. if an rjmp or jmp instruction is not present at address $000, the part is placed into a ? no program ? reset state. this is to pro- tect the part from fetching instructions when no program is pres ent. interrupt response time the interrupt execution response for all the enabled avr interrupts is a mini mum of four clock cycles. after the four clock cycles, the program vec tor address for the actual inter- rupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stack. the vector is a jump to the interrupt routine, and this jump takes two clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is comple ted before the interrupt is ser ved. a return from an interrupt handling routine takes four clock cycles. during these four clock cycles, the program counter is popped back from the stack. when avr exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note: the status register (sreg) is not saved by the avr hardware. this must be performed by user software when required. memory programming program memory lock bits the AT86RF401 microtransmitter provides two lock bits that can be left unprogrammed ( ? 1 ? ) or can be programmed ( ? 0 ? ) to obtain the additional features listed in table 6. note: the lock bits can only be erased with the chip erase opera tion. in-system flash and eeprom the AT86RF401 offers 2 kbytes (1k x 16) of in-system reprogrammable flash program memory and 128 bytes of eeprom data memory. this memory can be programmed serially via the spi interface. spi interface both the program and data memory arrays can be programmed using the serial spi bus while resetb is pulled to gnd. the serial interface consists of pins sck, sdi (input) and sdo (output). when programming, an au to-erase cycle is built into the se lf-ti med p rogramming opera- tion, and there is no need to first e xecute the chip e rase instruction. the chip e rase operation sets every memory location in the eeprom array to $ff. either an external system clock is supplied at pin xtal/clk or a crystal needs to be connected across pins xtal/clk and xtalb. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: 4 xtal clock cycles high: 16 xtal clock cycles ta ble 6. lock bit protection modes program lock bits protection type mod e lb1 lb2 1 1 1 no program lock features 201 further serial (spi) programming of the eeprom is disabled (both program and data memory). 3 0 0 same as mode 2, but verify is also dis abled 14 AT86RF401 1424f ? rke ? 12/03 serial programming algorithm refer to figure 4 (page 15), figure 5 (page 16) and figure 6 (page 17). to program and verify the AT86RF401 in the serial programming mode, the following sequence is recommended. power-up sequence: 1. apply power between vdd and gnd while resetb and sck are set to ? 0 ? . if a crystal is not connected across pins xtal and xtalb, apply a clock signal to the xtal pin. if the programmer can not guarantee that sck is held low during power-up, resetb must be given a positive pulse after sck has been set to ? 0 ? . 2. wait for at least 20 ms and enable serial programming by sending the program- ming enable instruction to pin sdi. this must occur prior to any program/erase operations. 3. if a chip erase is performed, wait 4 ms, give resetb a positive pulse and start over again from step 2. 4. the array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. the memory location is first auto- matically erased before new data is written. the next byte can be written after 4ms. 5. any memory location can be verified by using the read instruction, which returns the content at the selected address at serial output sdo. 6. at the end of the programming session, resetb must be set high to commence normal operation. signature bytes all atmel microcontrollers have a three-byte signature code that identifies the device. for the AT86RF401, the signature bytes are: 0x000: 0x1e (indicates manufactured by atmel) 0x001: 0x91 (indicates 2 kbytes flash program memory) 0x002: 0x81 (indicates AT86RF401 when 0x001 is 0x91) 15 AT86RF401 1424f ? rke ? 12/03 data eeprom access from the avr note: a = address high bits b = address low bits h = 0: low byte, 1: high byte o = data out i = data in x = don ? t care 1 = lock bit 1 2 = lock bit 2 figure 4. serial programming and verify notes: 1. when writing , data is clocked on the rising edge of clk. 2. when reading , data is clocked on the falling edge of clk. see figure 5 for an explanation. table 7 . AT86RF401 serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte 4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after resetb goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom read program memory 0010 h 000 0000 00 aa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a:b write program memory 0100 h 000 0000 00 aa bbbb bbbb iiii iiii write h (high or low) data i to program memory at word address a:b read eeprom memory 1010 0000 0000 0000 x bbb bbbb oooo oooo read data o from eeprom memory at address b write eeprom memory 1100 0000 0000 0000 x bbb bbbb iiii iiii write data i to eeprom memory at address b write lock bits 1010 1100 111x x 21 x xxxx xxxx xxxx xxxx write lock bits. set bits 21 = ? 0 ? to program lock bits. i/o read 10110000 0000 0000 00bbbbbb oooo oooo read data 0 from i/o memory address b i/o write 11010000 0000 0000 00bbbbbb iiii iiii write data i to i/o memory address b read signature byte 0011 0000 000x xxxx xxxx xxbb oooo oooo bat sck sdo sdi resetb xtal xtalb 2.0?3.5v clock in data out instr. in, data in gnd 6 to 20 mhz AT86RF401 16 AT86RF401 1424f ? rke ? 12/03 figure 5. serial programming waveforms note: this device includes an integrated 128-byte eeprom, which is accessed by three registers located in the i/o memory space. these are the deecr, deedr and deear registers. for more information, refer to i/o register description. avr c ore architectural over view the fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single cl ock cycle access time. this means that during one single clock cycle, one arithmetic logic unit (alu) operation is executed. two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing, enabling effici ent address calculations. one of the three address pointers is also used as the address pointer for look-up tables in flash program memory. these added function registers are the 16-bit x-register, y-register and z- register. the alu supports arithmetic and logic operations between registers or between a con- stant and a register. single register operations are also executed in the alu. figure 6 shows the AT86RF401 avr architecture. in addit ion to the register operation, the conventi onal memory addressing modes can be used on the register file as well. this is enabled by the fact that the register file is assigned the 32 lowest data space addre sses ($00 ? $1f), allowing them to be accessed as though they were ordinary memory locations. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, timer/counters, a/d converters and other i/o functions. the i/o memory can be accessed directly or as the data space locations following t hose of the register file, $20 ? $5f. serial data input (sdi) serial data output (sdo) serial clock input (sck) msb msb lsb lsb 17 AT86RF401 1424f ? rke ? 12/03 figure 6. avr core architecture the avr uses a harvard architecture concept, with separate memories and buses for program and data. the program memory is executed with a two-st age pipeline. while one instruction is being executed, the next instruction is pr efetched from the program memory. this concept enables instructions to be executed in every clock cycle. the pro- gram memory is in-system, reprogrammable flash memory. with the jump and call instructions, the whole 1k word address space is directly accessed. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return add ress program c ounter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the 7-bit stack pointer sp is read/write accessible in the i/o space. the 128-byte data sram can be easily accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all li near and regular me mory maps. 1k x 16 program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registers alu status and control bit timer spi unit programmable clock divider 128 x 8 eeprom data bus 8-bit brown-out/low battery detector 128 x 8 data sram direct addressing indirect addressing rf transmitter watchdog timer 6 i/o lines 18 AT86RF401 1424f ? rke ? 12/03 a flexible interrupt module has its control registers in the i/o space with an ad ditional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. the inter- rupts have priority in accordance with their interrupt vector position; the lower the interrupt vector address, the hi gher the priority. figure 7. memory maps $000 $3ff program memory application flash section 19 AT86RF401 1424f ? rke ? 12/03 general-purpose register file figure 8 shows the structure of the 32 general -purpose work ing registers in the cpu. figure 8. avr cpu general-purpose working registers all the register operating instructions in the instruction set have direct and single cycle access to all registers. the only exception is the five constant arithmetic and logic instructions (sbci, subi, cpi, andi and ori) between a constant and a register, and the ldi instruction for load immediate constant data. these instructions apply to the second half of the registers in the register file, r16...r31. the general sbc, sub, cp, and and or and all other operations between two registers or on a single register apply to the entire register file. as shown in figure 9, each register is also assigned a data memory address, m apping the registers directly into the first 32 locations of the user data space. although not being physically implemented as sram locations, this memory organization provides great flexibility in access of the registers, as the x, y and z registers can be set to index any register in the file. 7 0 addr. r0 $00 r1 $01 r2 $02 ? r13 $0d r14 $0e r15 $0f r16 $10 r17 $11 ? r26 $1a x-register low byte r27 $1b x-register high byte r28 $1c y-register low byte r29 $1d y-register high byte r30 $1e z-register low byte r31 $1f z-register high byte 20 AT86RF401 1424f ? rke ? 12/03 the x, y and z registers the registers r26...r31 have some added functions to their general-purpose usage. these registers are address pointers for indirect addressing of the data space. the three indirect address registers x, y and z are defined as shown in figure 9. figure 9. the x, y and z registers in the different addressing modes, these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). arithmetic logic unit (alu) the high-performance avr alu operates in direct connection with all the 32 general- purpose working registers. within a single clock cycle, alu operations between regis- ters in the register file are executed. the alu operations are divi ded into three main categories: arithmetic, logical and bit-functions. the multiplier is not present in this ver- sion of the core. therefore, the mul instruction is not supported. in-system self- programmable flash program memory the AT86RF401 contains 2 kbytes of on-chip flash memory for program storage. since all instructions are 16- or 32-bit words, the flash is organized as 1k x 16. the flash memory has an endurance of at least 1000 write/erase cycles. the pc is 10 bits wide, thus addressing the 1024 program memory locations. see the memory pro- gramming section (page 13) for a detailed description on flash data serial downloading. constant tables can be allocated within the entire program memory address space (see table 22, instruction set, page 45). 15 xh xl 0 x register 70 0 7 0 r27 ($1b) r26 ($1a) 15 yh yl 0 y register 70070 r29 ($1d) r28 ($1c) 15 zh zl 0 z register 70 0 7 0 r30 ($1f) r31 ($1e) 21 AT86RF401 1424f ? rke ? 12/03 sram data memory figure 10 shows how the AT86RF401 sram memory is organized. figure 10. sram organization the lower 224 data memory locations address the register file, the i/o memory and the internal data sram. the first 96 locations address the register file + i/o memory, and the next 128 locati ons address the in ternal data sram. the five different addressing modes for the data memory cover: direct, indirect with dis- placement, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode features a 63 address locations r each from the base address given by the y or z register. when using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers x, y and z are decremented and incremented. the 32 general-purpose working registers, 64 i/o registers and the 128 by tes of internal data sram in the AT86RF401 are all accessible through all these addressing modes. program and data addressing modes the AT86RF401 avr enhanced risc microcontroller supports powerful and efficient addressing modes for access to the program memory (flash) and data memory (sram, register file and i/o memory). this section describes the different addressing modes supported by the avr architecture. in the figures, op means the operation code part of the instruction word. to simplify, not all figures show the exact location of the address- ing bits. register file r0 r1 r2 r29 r30 r31 i/o registers $00 $01 $02 ... $3d $3e $3f ... $0000 $0001 $0002 $001d $001e $001f $0020 $0021 $0022 ... $005d $005e $005f ... data address space $0060 $0061 $00de $00df ... internal sram 22 AT86RF401 1424f ? rke ? 12/03 register direct, single register rd figure 11. direct single register addressing the operand is contained in register d (rd). register direct, two registers rd and rr figure 12. direct register addressing, two registers operands are contained in register r (rr) and d (rd). the result is stored in register d (rd). i/o direct figure 13. i/o direct addressing operand address is contained in 6 bits of the instruction word. ? n ? is the destinat ion or source register address. 23 AT86RF401 1424f ? rke ? 12/03 data direct figure 14. direct data addressing a 16-bit data address is contained in the 16 lsbs of a two-word instruction. rd/rr specify the destination or source register. data indirect with displacement figure 15. data indirect with displacement operand address is the result of the y or z register contents added to the address con- tained in 6 bits of the instruction word. data indirect figure 16. data indirect addressing operand address is the contents of the x, y or z register. op rr/rd 16 31 15 0 16 lsbs $00 $df 20 19 data space data space $00 $df y or z - register op a n 0 0 5 6 10 15 15 data space $0000 $df x, y or z - register 0 15 24 AT86RF401 1424f ? rke ? 12/03 data indirect with pre-decrement figure 17. data indirect addressing with pre-decrement the x, y or z register is decremented before the operation. operand address is the decremented contents of the x, y or z register. data indirect with post-increment figure 18. data indirect addressing with post-increment the x, y or z register is incremented after the operation. operand address is the con- tent of the x, y or z register prior to incrementing. constant addressing using the lpm instruction figure 19. code memory constant addressing constant byte address is spe cified by the z register contents. the 10 msbs select word address (0 ? 1k). for lpm, the lsb selects low byte if cleared (lsb = 0) or high byte if set (lsb = 1). data space $0000 $df x, y or z - register 0 15 -1 data space $0000 $df x, y or z - register 0 15 1 $3ff 25 AT86RF401 1424f ? rke ? 12/03 indirect program addressing, ijmp and icall figure 20. indirect program memory addressing program execution continues at address contained by the z register (i.e., the pc is loaded with the contents of the z register). relative program addressing, rjmp and rcall figure 21. relative program memory addressing program execution continues at address pc + k + 1. the relative address k is from ? 2048 to 2047. $3ff $3ff 1 26 AT86RF401 1424f ? rke ? 12/03 eeprom data memory the AT86RF401 contains 128 bytes of data eeprom memory. it is or ganized as a sep- arate data space in which single bytes can be r ead and writt en. the acc ess between the eeprom and the cpu is described in the memory programming section (p age 13). memory access times and instruction execution timing this section describes the general access timing concepts for instruction execution and internal memory access. the avr cpu is driven by the system clock ? generated from the main oscillator for the chip. a programmable clock divider generates this clock from the crystal oscillator input. figure 22 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipe- lining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit. figure 22. the parallel instruction fetches and instruction executions figure 23 shows the internal timing concept for the register file. in a single clock cycle, an alu operation using two register operands is executed, and the res ult is stored back to the destination register. figure 23. single cycle alu operation system clock ? 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 system clock ? total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 27 AT86RF401 1424f ? rke ? 12/03 the internal data sram access is performed in two system clock cycles as described in figure 24. figure 24. on-chip data sram access cycles all i/os and peripherals are placed in the i/o space. the i/o locati ons are accessed by the in and out instructions, transferring data between the 32 general-purpose working registers and the i/o space. i/o registers within the address range $00 ? $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. refer to table 10, ? instruction set manual, ? on page 44 for more details. when using the i/o specific com- mands in and out, the i/o addresses $00 ? $3f must be used. when addressing i/o registers as sram, $20 must be added to these addresses. for compatibility with future devices, reserved bits should be written to ? 0 ? if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical ? 1 ? to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a ? 1 ? back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers $00 to $1f only. the i/o and peripherals control regis ters are explained in the following sections. system clock ? write read data data address address t1 t2 t3 t4 prev. address read write 28 AT86RF401 1424f ? rke ? 12/03 i/o memory the i/o space definition of the AT86RF401 is shown in table 8 below. note: reserved and unused locati ons are not shown in the table. table 8 . AT86RF401 i/o space definitions address hex name function $3f sreg status register $3e sph stack pointer high register (program to 0 x 00) $3d spl stack pointer low register $35 bl_config battery low configuration register $34 b_det button detect register $33 avr_config avr configuration register $32 io_datin i/o data in register $31 io_datout i/o data out register $30 io_enab i/o enable register $22 wdtcr watchdog timer control register $21 btcr bit timer control register $20 btcnt bit timer count register $1e deear data eeprom address register $1d deedr data eeprom data register $1c deecr data eeprom control register $17 lockdet2 lock detector configuration register 2 $16 vcotune vco tuning register $14 pwr_atten power attenuation control register $12 tx_cntl transmitter control register $10 lockdet1 lock detector configuration register 1 29 AT86RF401 1424f ? rke ? 12/03 i/o and control registers the AT86RF401 i/os and peripherals are placed in the i/o space. the various i/o loca- tions are accessed by the in and out instructions transferring data between the 32 general-purpose working registers and the i/o space. i/o registers within the address range $00 ? $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instruc- tions. refer to table 22 on page 45 for more details. the different i/o and peripherals control registers are explained in the following sections. transmitter control register descriptions lock detector configuration register 1 ? lockdet1 bits[7:5] reserved. bit[4]: upok if set high, this bit resets the unlock counter. the bit is level sensitive, and the unlock counter will not count unless this bit is set to ? 0 ? . leaving this bit high essentially dis- ables the unlock detector. bit[3]: enko (enable key on bit) if set to ? 1 ? , the rising edge of txk starts the blackout period, during which any c ycle slips are ignored and do not affect the unlock circuit. bit[2]: bod (black out disable) when set high, cycle slips are counted immediately but only if lock is asserted high (tx_cntl b[2]). bits[1:0] cs[1:0]: cycle slip counter these two bits determine how many cycle slips are allowed before the lo ckdetect signal is set low. the cycle slips are not counted unless the blackout logic is either dis- abled or the blackout window has passed. ta ble 9. cycle slip counter definition bit 7 6 5 4 3 2 1 0 $10 ? ? ? upok enko bod cs1 cs0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 cs[1:0] functionality 00 1 cycle slip causes unlock condition 01 2 cycle slips cause unlock condition 10 3 cycle slips cause unlock condition 11 4 cycle slips cause unlock condition 30 AT86RF401 1424f ? rke ? 12/03 transmit control register ? tx_cntl bit[7:6] reserved. bit[5]: txe, transmitter enable this bit, when set, turns on the phase locked loop (pll) rf frequency synthesizer but should not be used to modulate the rf carrier or excessive spurious noise may result. bit[4]: txk, transmitter key this bit, when set, turns on the rf power amplifier. it should be used to modul ate the rf carrier manually. this bit should be cleared when the bit timer is configured in trans- mit mode. figure 25. modulation control logic bit[3] reserved. bit[2]: loc, pll lock this bit is set when the f requency synthesizer in the transmitter is locked. typically, the programmer should test the status of this bit to insure the rf carrier is s table prior to turning on the rf power amplifier. power attenuation control register ? pwr_atten this register is used to select the power attenuation level. the total power attenuation is the sum of the coarse attenuation and fine attenuation. as an example, to obtain 15 db of attenuation, the coarse setting of 12 db and fine setting of 3 db would be select ed. to obtain 12 db coarse attenuation, bits[5:3] would be set to [010]. to obtain 3 db of fine attentuation would require bits[2:0] to be set to [011]. note: maximum rf output power occurs when bits[5:0] = [000000]. bits[7:6] reserved bit 7 6 5 4 3 2 1 0 $12 ? ? txe txk ? loc ? ? read/write r/w r/w r/w r/w r/w r r/w r/w initial value 0 0 0 0 0 0 0 0 bit timer txk on/off power amp pll rf in rf out bit 7 6 5 4 3 2 1 0 $14 ? ? pcc2 pcc1 pcc0 pcf2 pcf1 pcf0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 31 AT86RF401 1424f ? rke ? 12/03 bits[5:3]: pcc, power control (coarse) attenuates the output power in 6 db steps. table 10. coarse power control definition bits[2:0]: pcf, power control (fine) attenuates the output power in 1 db steps. table 11. fine power control definition vco tuning register 6 ? vcotune note: * these values are unknown at initial startup. bits[4:0]: vco tuning capacitor array this device requires the use of an external inductor to tune the vco. tolerance of the inductor, coupled with process variation of the device, can lead to variations in the tun- ing point of the vco. a switched array of tuning capacitors has been added internally to the device in order to ? fine tune ? the vco. this capacitance is switched across pins 3 and 4 (l1 and l2) of the device. the capacitor array is set by vcotune[4:0] and is comprised of the following switched capacitance levels: pcc[5:3] output attenuation 000 0 db 001 6 db 010 12 db 011 18 db 100 24 db 101 30 db 110 invalid 111 invalid pcf[2:0] output attenuation 000 0 db 001 1 db 010 2 db 011 3 db 100 4 db 101 5 db 110 invalid 111 invalid bit 7 6 5 4 3 2 1 0 $16 vcovdet[1] vcovdet[0] ? vcotune[4] vcotune[3] vcotune[2] vcotune[1] vcotune[0] read/write r r r/w r/w r/w r/w r/w r/w initial value * * 0 0 0 0 0 0 32 AT86RF401 1424f ? rke ? 12/03 table 12. vco tuning capacitor definition vcotune[4:0] capacitance (pf) 00000 0 00001 0.03 00010 0.06 00011 0.09 00100 0.12 00101 0.15 00110 0.18 00111 0.21 01000 0.24 01001 0.27 01010 0.30 01011 0.33 01100 0.36 01101 0.39 01110 0.42 01111 0.45 10000 0.48 10001 0.51 10010 0.54 10011 0.57 10100 0.60 10101 0.63 10110 0.66 10111 0.69 11000 0.72 11001 0.75 11010 0.78 11011 0.81 11100 0.84 11101 0.87 11110 0.90 11111 0.93 33 AT86RF401 1424f ? rke ? 12/03 bits[7:6]: vco voltage detector the vco voltage detector circuit monitors the level of the vco control voltage. this cir- cuit, along with the vco switch caps and the lock detect circuit, is intended for use with a software algorithm to tune the vco such that the vco control voltage is centered approximately at 1.1v. the voltage detector circuit consists of two comparators with fixed reference voltages of v1 (lower reference voltage) and v2 (upper reference voltage). the vco control voltage is compared to these two reference voltages and generates the state table listed in table 13. the state of these comparators is output to bits 7 and 6 (vcodet[1:0]) of the vcotune register. lock detector configuration register 2 ? lockdet2 bit[7]: eud a ? 1 ? enables the unlock detect logic. bit[6]: lat (lock always true) forces the lockdetect signal to ? 1 ? at the output of the lock detect circuitry. this may be useful if the lock detect signal is not going high for some reason, and a power amp inter- lock has been implemented, and the user wishes to enable the power amp output stage. table 13. vco window comparator states vcovdet[1:0] vco control voltage 00 above lower comparator threshold and below up per comparator threshold. control voltage is within the valid window of operation. 01 below both thresholds. control voltage is outside the recommended window of operation. 10 above both thresholds. control voltage is outside the recommended window of operation. 11 not a valid state. bit 7 6 5 4 3 2 1 0 $17 eud lat ulc[2] ulc[1] ulc[0] lc[2] lc[1] lc[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 34 AT86RF401 1424f ? rke ? 12/03 bit[5:3]: ulc[2:0] the unlock count (ulc) bits count a certain number of refere nce clocks, after which the unlock detect circuit looks for a number of cycle slips determined by cs[1:0] before making the loc detect signal go low. the ulc bits essentially control the blackout period of the unlock detect circuit. the unlock counter is reset by the key signal rising (if enko is asserted), or by the loc rising edge, or by the upok signal being set high. table 14. pll unlock counter definition bits[2:0]: lc[2:0] the lock count (lc) bits control a counter that, after a number of reference clocks, cause lock detect to go high. this counter will reset if a cycle slip or a reset signal occurs (which happens if txe goes low), if an out-of-lock condition occurs, if the crystal osci lla- tor frequency is too low, or if the vco feedback frequency is too low. table 15. pll lock counter definition ulc[2:0] number of ref clocks of delay 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 lc[2:0] number of ref clocks of delay 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 35 AT86RF401 1424f ? rke ? 12/03 eeprom control register descriptions data eeprom control register ? deecr bits[7:4] reserved. these bits should be ? 0 ? when written; otherwise, results will be unpredictable. bit[3]: eeprom busy bit initially set to ? 0 ? . this bit w ill be set high during writes to the eeprom. bit[2]: eeprom unlock bit set this bit to ? 1 ? before writing the eeprom. reset this bit to ? 0 ? after the write is com- plete. this bit should be left in the zero state when the eeprom is not being used, which will protect the eeprom data during power transients. bit[1]: eeprom load bit to write the eeprom, use the following procedure: note: because of noise and power considerations, the eeprom should not be written while the transmitter is enabled. 1. set the unlock bit. 2. write the address of the first byte to the deear. 3. set the load bit. this locks the page address in the deear. keep the unlock bit set. 4. write the desired data to the deedr register. this byte is loaded into the eeprom and will be written when the load bit is later deasserted. 5. if it is desired to write another byte in the same page, write the new address to the deear register, and a new byte to the deedr register. continue until all bytes that are to be written are loaded into the eeprom. bytes may only be loaded to an address once. there are eight bytes per page. 6. deassert the load bit. this starts the write operation. some time after load is deasserted, the busy bit will go high. another r ead or write operation may not be started until the busy bit has returned to ? 0 ? . writes take approximately 4 ms to complete. again, the unlock bit must still be set w hen deassert ing the l oad bit. 7. after all writes are complete, write ? 0 ? to the unlock bit. bit[0]: eeprom read bit to read the eeprom use the following procedure: 1. write the address to the deear. 2. set the read bit. 3. read the data register. the read bit will reset itself. 4. if another read needs to be done, repeat steps 1 ? 3 again. bit 7 6 5 4 3 2 1 0 $1c ? ? ? ? bsy eeu eel eer read/write r/w r/w r/w r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 36 AT86RF401 1424f ? rke ? 12/03 data eeprom data register ? deedr bits[7:0] this register contains the byte to be written to eeprom. if a r ead operation has been done, this register contains that last byte read from the data eeprom. data eeprom address register ? deear bit[7] reserved. bits[6:3]: data eeprom page address these bits select the page in the eeprom that is to be accessed. these bits are write locked and cannot be altered when the load bit is set. bits[2:0]: data eeprom byte address these bits select the byte in the page that is to be accessed. during a page wr ite opera- tion, these bits are used in combination with the deedr register to write bytes into a page. bit 7 6 5 4 3 2 1 0 $1d ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $1e ? pa 6 pa 5 pa 4 pa 3 ba2 ba1 ba0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 37 AT86RF401 1424f ? rke ? 12/03 bit timer register descriptions bit timer count register ? btcnt bit [7:0] lowest 8 bits of countval . when combined with bits [7:6] of the btcr register, countval determines a counter value that sets the width of a mark or a space that is sent to the transmitter. the width of the mark or space is: p xx = p avr * (countval +1) where p xx is the period of the mark or space, and p avr is the period of the avr clock that is determined by the acs bits of the avr configuration register, avr_config. bit timer control register ? btcr bit[7:6] count_val[9:8]. msb of btcnt counter value bits. bits[5:4] table 16. bit timer mode. bit[3]: interrupts enabled if this bit is set, the flag2 and flag0 will g enerate their respective interrupts when they are set. flag0 interrupt vector is located at 0 x 04. flag2 interrupt vector is located at 0 x 02. typically, a jmp instruction resides at these vector locations to pass control to an interrupt handler. for flag0 only, slightly faster execution can be achieved if the jmp instruction is eliminated, and the interrupt service routine is located beginning at 0 x 04. bit 7 6 5 4 3 2 1 0 $20 c7 c6 c5 c4 c3 c2 c1 c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $21 c9 c8 m1 m0 ie f2 data f0 read/write r/w r/w r/w r/w r/w r r/w r initial value 0 0 0 0 0 0 0 0 mode[1:0] bit timer function 00 bit timer disabled 01 bit timer in generic timer/counter mode 10 bit timer in receive mode 11 bit timer in transmit mode 38 AT86RF401 1424f ? rke ? 12/03 bit[2]: flag2 in transmit mode, this flag indicates the transmit done condition that occurs when the buffer is empty and the counter has counted down to ? 0 ? . in receive mode, this flag indi- cates that an edge has occurred, and the avr should proc ess the count value in the btcr and btcnt registers. this bit is cleared upon read, e.g., in r16, btcr. table 17. bit timer flag2 definition bit[1]: data bit in transmit mode, this is a one-bit buffer that the avr writes data to and the bit timer extracts data from. when the bit timer removes the value from this register, the flag0 bit is set, and if enabled, an interrupt (int2) is generated. if the interrupt is used, the isr should load a new bit into the buffer. if the interrupt is not enab led, then a polling method should be used to detect flag0 being set. because of overhead associated with interrupt handling, it may be slightly faster to use polling. in receive mode, the value in this register indicates whether the edge at the io3 pin was rising or falling. a ? 1 ? indi cates a rising edge occurred, and a ? 0 ? indicates that a falling edge was detected. the number of avr clock cycles since the last edge is held in the c[9:0] ( countval ) bits (that is, unless an overflow condition has occurred). bit[0]: flag0 in transmit mode, this flag indicates the buffer is empty and the avr should load new data into it. in receive mode, this indicates a counter overflow condition has occurred. the avr should increment its software counter if this condition has occurred. this bit is cleared upon read, e.g., in r16, btcr. watchdog timer control register ? wdtcr bits[7:5] reserved. these bits will always read as ? 0 ? . bit[4]: wdtoe, watchdog turn-off enable this bit must be set ( ? 1 ? ) when the wde bit is cleared. otherwise, the watchdog will not be disabled. once set, hardware will clear this bit to ? 0 ? after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. bit[3]: wde, watchdog enable mode[1:0] flag2 function 00 disabled 01 indicates transmit done condition; buffer is empty and the counter has expired. 10 an edge has been detected at the io3 pin. 11 indicates transmit done condition; buffer is empty and the counter has expired. bit 7 6 5 4 3 2 1 0 $22 ? ? ? wdtoe wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 39 AT86RF401 1424f ? rke ? 12/03 when the wde is set ( ? 1 ? ), the watchdog timer is enabled, and if the wde is cleared ( ? 0 ? ), the watchdog timer function is disabled. wde can only be cleared if the wdtoe bit is set ( ? 1 ? ). to disable an enabled watchdog timer, the following procedure must be followed: in the same operation, write a l ogical ? 1 ? to wdtoe and wde. a logical ? 1 ? must be written to wde even though it is set to ? 1 ? before the disable operation starts. within the next four clock cycles, write a logical ? 0 ? to wde. this disables the wat chdog. bits[2:0]: wdp2, wdp1, wdp0, watchdog timer prescaler 2, 1 and 0 the wdp2, wdp1 and wdp0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding time-out periods are shown in table 18. note: example: if the crystal period is 50 ns and the system clock divider is set to 32 (b its[7:5] in the pwr_ctl register are set to 010) and the wdt prescaler is set to 32k, then: watchdog timeout = 50 ns 32 32768 = 52 ms i/o enable register ? io_enab bit[7] reserved. bit[6] if set to ? 1 ? , additional hysteresis is added to the battery low and brown-out logic. see bl_config register description and table 21 on page 43 for more details. table 18. watchdog timer prescale select wdp2 wdp1 wdp0 number of system clock cycles 0 0 0 2,048 cycles 0 0 1 4,096 cycles 0 1 0 8,192 cycles 0 1 1 16,384 cycles 1 0 0 32,768 cycles 1 0 1 65,536 cycles 1 1 0 131,072 cycles 1 1 1 262,144 cycles t wdt xtalb period acs div wdt div = bit 7 6 5 4 3 2 1 0 $30 ? bohyst ioe5 ioe4 ioe3 ioe2 ioe1 ioe0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 40 AT86RF401 1424f ? rke ? 12/03 bits[5:0] if set to ? 1 ? , the corresponding bit (pin) io[5:0] is confi gured as an output. data may then be written to that output by writing to the io_data register. if set to ? 0 ? , the cor resp ond- ing bit (pin) may be either a button input (refer to the button detect register, $34) used to wake the part up or a normal digital i nput. table 19. i/o pin definition i/o data out register ? io_datout bits[7:6]: reserved these bits read ? 0 ? . bits[5.0] if enabled in the io_enab register and not in test mode, the data in bits[5:0] goes to the corresponding general-purpose output io [5:0]. i/o data in register ? io_datin bits[7:6]: reserved this bit reads ? 0 ? . bits[5:0] these bits directly read the data from the i/o pins io[5:0]. writes to these bits have no effect. avr configuration register ? avr_config io_enab[n] io_datout[n] io[n] 0 0 normal input 0 1 button input 1 0 output driven low 1 1 output driven high bit 7 6 5 4 3 2 1 0 $31 ? ? ioo5 ioo4 ioo3 ioo2 ioo1 ioo0 read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $32 ? ? ioi5 ioi4 ioi3 ioi2 ioi1 ioi0 read/write r/w r/w r r r r r r initial value 0 0 bit 7 6 5 4 3 2 1 0 $33 ? acs1 acs0 tm bd bli sleep bbm read/write r/w r/w r/w r/w r r w r/w initial value 0 0 0 0 0 0 0 0 41 AT86RF401 1424f ? rke ? 12/03 bits[6:5]: avr system clock select these bits select the divide value of the xtalb input that is used to produce the avr system clock. table 20. avr clock select definition this clock select value may be programmed on the fly by either the avr processor in normal operation or by an i/o write spi command during spi mode. note that during spi mode, the i/o and serial programming logic runs at xtalb/16 fr equency. bit[4]: test mode when this bit is set to ? 1 ? , the part enters test mode. the i/o pins, if enabled, assume the following functionality: notes: 1. io_enab register is not used for spi pins. 2. in spi mode, the i/o registers may be directly accessed via the spi interface. txkey, lockdetect may be output using this mode. bit[3]: battery dead indicates battery is dead. only readable by spi interface. bit[2]: battery low indicator this bit is identical to bit[7] of battery low configuration register ($35). when bit[6] of battery low configuration regis ter ($35) is set (battery low valid), a set bit in this loca- tion indicates that the battery voltage is lower t han the voltage level that is determ ined by bits[5:0] of battery low configuration register ($35). bit [1]: sleep bit when set, this bit stops the crystal oscillator. this stops the avr processor with the pro- gram counter frozen at the current instruction. sleep will a lso s top the watchdog timer. the watchdog timer is only restarted if the part wakes up. if an i/o pin is configured as a button, a button press will start the osc illator and check the battery level. if the battery level is greater than the battery dead level, the avr system cl ock is started and no rmal program execution continues. if the battery level is below the battery dead level, the crystal oscillator is turned off, putting the part back to sleep until a button is pressed again (care should be taken not to put the part to sleep unless a button is configured and enabled). bit[0]: button boot mode (bbm) if the bbm bit is set and the part is brought out of sleep mode by a button input activa- tion, the part will enter the button reset s tate. in this state, the part will reboot and begin acs[1:0] avr system clock 11 xtalb/16 10 xtalb/32 01 xtalb/64 00 xtalb/128 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 normal mode (resetb = 1) txkey (output) lockdetect (output) txenable (output) rfu rfu rfu spi mode (resetb = 0) txkey (output) lockdetect (output) txenable (output) spi_clk sdo sdi 42 AT86RF401 1424f ? rke ? 12/03 code execution at the reset location. this bit is reset at por and when exiting the button reset state. all other registers remain unchanged. button detect register ? b_det bits[7:6] reserved. these bits read ? 0 ? . bits[5:0] when an i/o pin is configured as a button using the io_enab and io_datout regis- ters and a logic low is detected on that pin, the button detect logic is activated. if the part is in sleep mode, the part responds as described in the avr configuration register description. if a good battery is present, the appropriate bit is set in this register. a bit in this register is cleared by writing a ? 0 ? to it. battery low configuration register ? bl_config bit[7]: battery low when bit[6] in this register is set (battery low valid), the bl (battery low) bit indicates that the battery voltage is lower than the vol tage level that is determ ined by bi t[5:0] of this register. it is important that the program mer also check bi t[6] (battery low valid) to be certain that this condition is valid. bit[6]: battery low valid when the battery low configuration register is written, this bit is set to ? 0 ? . when the battery voltage has been sampled and compared to the voltage determined by the blx bits, this bit is set to ? 1 ? indicating that the data in bit[7] (battery low) is valid. this can take up to 3100 xtal cycles to complete. note: the programmer should ensure that this bit is cleared prior to making a determina tion of the battery low status. this can be done by reloading bit[5] or directly clearing bit[6]. generally, the programmer loads bit[5], loops until bi t[6] is set, and then checks bit[3] to determine the status of the battery. bit[5:0]: battery low detection level this value is sent to the battery monitor. the threshold is calcula ted us ing the formulas shown in table 21 on page 43. note: this threshold can be set below the brown-out voltage level. bit 7 6 5 4 3 2 1 0 $34 ? ? bd5 bd4 bd3 bd2 bd1 bd0 read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $35 bl blv bl5 bl4 bl3 bl2 bl1 bl0 read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 43 AT86RF401 1424f ? rke ? 12/03 table 2 1. low battery detection threshold formulas (v ref is approximately 0.7 volts) v dd falling v dd rising bohyst = 1 (large hysteresis) bohyst = 0 (small hysteresis) vdd 3.887 v ref 1 0.887 63 -------------- - bl[5:0] + ---------------------------------------------------------- - = vdd 4.05 v ref 1 0.887 63 -------------- - bl[5:0] + ---------------------------------------------------------- - = vdd 4.22 v ref 1 0.887 63 -------------- - bl[5:0] + ---------------------------------------------------------- - = bl[5:0] 71 3.887 v ref v dd ------------- 1 ? = bl[5:0] 71 4.05 v ref v dd ------------ - 1 ? = bl[5:0] 71 4.22 v ref v dd ------------ - 1 ? = 44 AT86RF401 1424f ? rke ? 12/03 the stack pointer ? sp the stack pointer is implemented as two 8-bit registers in the i/o space locations $3e ($5e) and $3d ($5d). caution: as the data memory has 224 locations, only 8 bits are used and the sph register must be programmed to 0 x 00. the stack pointer points to the data sram stack area where the subroutine and inter- rupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above $60. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed o nto the stack with subroutine call and interrupt. the stack pointer is incremented by one w hen data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine (ret) or return from interrupt (reti). the status register ? sreg the avr status register ? sreg ? at i/o space location $3f is defined as: bit[7] ? i: global interrupt enable the global interrupt enable bit must be set ( ? 1 ? ) for the interrupts to be enabled. the individual interrupt enable control is then performed in the interrupt mask registers (gimsk/timsk). if the global interrupt enable register is cleared ( ? 0 ? ), none of the inter- rupts are enabled, independent of the gimsk/timsk values. the i-bit is cleared by hardware after an interrupt has occurred and is set by the reti instruction to enable subsequent interrupts. bit[6] ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source and destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. bit[5] ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. see figure 10 on page 21 for detailed information. bit 15 14 13 12 11 10 9 8 $3e ????? sp10 sp9 sp8 sph $3d sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write rrrrrr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 00000000 bit 76543210 $3f ithsvnzc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 45 AT86RF401 1424f ? rke ? 12/03 bit[4] ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two ? s comple- ment overflow flag v. see table 22 for detailed information. bit[3] ? v: two ? s complement overflow flag the two ? s complement overflow flag v supports two ? s complement arithmetics. see table 22 below for detailed information. bit[2] ? n: negative flag the negative flag n indicates a negative result after the different arithmetic and logic operations. see table 22 below for detailed information. bit[1] ? z: zero flag the zero flag z indicates a zero result after the different arithmetic and logic operations. see table 22 below for detailed information. bit[0] ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see table 22 for detailed information. table 2 2. instruction set mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 1 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 2 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from register rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 1 and rd, rr logical and registers rd rd ? rr z,n,v 2 andi rd, k logical and register and constant rd rd ? kz,n,v1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one ? s complement rd $ff ? rd z,c,n,v 1 neg rd two ? s complement rd $00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? ($ff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 46 AT86RF401 1424f ? rke ? 12/03 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 1 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc k none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 call k direct subroutine call pc k none 3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? cz, n,v,c,h1 cpi rd,k compare register with immediate rd ? kz, n,v,c,h1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag set if (v = 1) then pc pc + k + 1 none 1/2 table 2 2. instruction set (continued) mnemonics operands description operation flags #clocks 47 AT86RF401 1424f ? rke ? 12/03 brvc k branch if overflow flag cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr + 1:rr none ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, ? x load indirect and pre-dec. x x ? 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, ? y load indirect and pre-dec. y y ? 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z + 1 none 2 ld rd, ? z load indirect and pre-dec. z z ? 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st ? x, rr store indirect and pre-dec. x x ? 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st ? y, rr store indirect and pre-dec. y y ? 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st ? z, rr store indirect and pre-dec. z z ? 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post- inc. rd (z), z z+1 none 3 in rd, p in port rd p none 1 table 2 2. instruction set (continued) mnemonics operands description operation flags #clocks 48 AT86RF401 1424f ? rke ? 12/03 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1 none 2 cbi p, b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c, rd(n+1) rd(n), c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c, rd(n) rd(n+1), c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0...6 z,c,n,v 1 swap rd swap nibbles rd(3...0) rd(7...4), rd(7...4) rd(3...0) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set two ? s complement overflow v 1v1 clv clear two ? s complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 nop no operation none 1 sleep sleep not implemented none 3 wdr watchdog reset (see specific description for wdr/timer) none 1 table 2 2. instruction set (continued) mnemonics operands description operation flags #clocks 49 AT86RF401 1424f ? rke ? 12/03 ordering information rf output ordering code package application temperature operating range 315 mhz AT86RF401u 20t north american ? 40 c to 85 c 434 mhz AT86RF401e 20t european ? 40 c to 85 c 264 to 456 mhz AT86RF401x 20t all applications ? 40 c to 85 c 50 AT86RF401 1424f ? rke ? 12/03 package drawing all devices are packaged on tape in reel; standard reel quantity is 2,500 pieces. 20a2 ? tsso 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 6/3/02 common dimensions (unit of measure = mm) symbol min nom max note d 6.40 6.50 6.60 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ?? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 20a2 , 20-lead (4.4 x 6.5 mm body), 0.65 pitch, thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. please refer to jedec drawing mo-153, variation ac, for additional information. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 20a2 c l1 a l d a2 e e1 e b top view side view end view 51 AT86RF401 1424f ? rke ? 12/03 data sheet change log please note that the page numbers referenced below apply to this document. changes from rev. 1424e-rke-03/03 to rev. 1424f-rke-9/03 updated text in low battery detection section on page 10. table 3, in low battery detection section on page 10 was moved to battery low configuration register section and became table 21 (page 43). updated text in battery low configuration register section (page 42). renumbered tables as required to maintain proper sequence. added data sheet change log section (page 51). replaced ? power control register ? with ? avr configuration register ? in button detect register section (page 42). removed references to cfil in figures 1, 2, and 3 and table 2. changed description of bit[2] (loc) in transmit control register section (page 30) from r/w to r and included additional descriptive text for bit[5], bit[4], and bi t[2]. added ? read signature byte ? command to serial programming instruction set shown in table 7 on page 15 and added signature bytes section on page 14. added note regarding maximum output power in power attenuation control register description section (page 30). added text to ? button reset ? paragraph in the reset sources section (page 12). added text to bit timer section (page 11). added text to bit timer control register section (page 37). printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the co mpany ? s standard warranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibil ity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi t hout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not auth orized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature 1424f ? rke ? 12/03 ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others. |
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